1. Field of the Disclosure
The present disclosure generally relates to memory devices and, more particularly, to a system and method to avoid DQS postamble ringing during memory writes.
2. Brief Description of Related Art
Memory devices are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 24 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 24 may constitute memory address pins or address bus 17, data (XDQ) pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17–19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address select (RAS) signal, a column address select (CAS) signal, an external data strobe (XDQS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 26. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 26 generally arranged in rows and columns to store data in rows and columns. A row decode circuit 28 and a column decode circuit 30 may select the rows and columns in the memory cells 26 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 26 is then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) circuit or I/O unit 32. The I/O circuit 32 may include a number of data output buffers to receive the data bits from the memory cells 26 (e.g., during a memory read operation) and provide those data bits or data signals to the corresponding data lines in the data bus 18. Alternatively, during a memory write operation, the I/O unit 32 may receive data bits externally supplied by a processor or memory controller (not shown) and may transfer or write the data bits into appropriate memory cells 26 using the externally supplied data strobe signal (XDQS) as discussed in more detail hereinbelow.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Access Strobe signal, a Column Access Strobe signal, a Write Enable signal, an external data strobe signal (XDQS), etc. The memory chip 12 communicates to other devices connected thereto via the pins 24 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 illustrates a prior art circuit showing how two bits of data (D0, D1) are written into appropriate memory cells 26 using the external strobe signal (XDQS) 19. It is noted here that for the sake of convenience the reference numeral “19” is used in the discussion below to refer to the XDQS signal or XDQS pin on the memory device 12. As discussed before, the XDQS pin is of course part of a set of control signal pins 19. However, because the following discussion is primarily related to the XDQS signal (as opposed to other control signals in the control bus 19), the reference numeral “19” is conveniently used to refer to the XDQS signal. This usage is for sake of convenience only and, does not, in any way, imply that the XDQS signal is the only control signal in the control bus 19. Furthermore, as FIG. 2 is illustrative in nature, only two bits of data (D0 and D1) are shown being written into memory cells 26. It is evident to one skilled in the art that the circuit shown in FIG. 2 may be replicated (e.g., by adding additional flipflops) for each data pin and for transferring or writing more than two data bits, as needed.
In FIG. 2, an external data pin (XDQ) 18 is shown to carry data bits to be written into memory cells 26. Again, as in the case with the designation of the XDQS pin, the reference numeral “18” is conveniently used to refer to one of the data pins—the XDQ signal or pin, instead of the entire data bus 18. It is evident that many more such XDQ pins 18 constitute the data bus. The data bits over the XDQ pin 18 are supplied to two data flipflops 36, 38, which are “strobed” or clocked by the external data strobe signal (XDQS) 19. Typically, the externally supplied strobe signal—the XDQS signal 19—is first received at an input buffer 34 in the I/O unit 32. The Enable control 40 of the buffer 34 allows controlled application of the XDQS signal 19 to the flipflops 36, 38. When the Enable control 40 is turned “on” or “activated”, the XDQS signal 19 is buffered through the buffer 34. On the other hand, turning “off” or deactivating the Enable control 40 may prevent further transmission of the XDQS signal 19 out of the buffer 34. In FIG. 2, the buffered XDQS signal 19 is designated as the DQS (data strobe) signal 39, which is the internal strobe signal that is used by the I/O unit 32 to strobe data on the XDQ pin 18 into appropriate memory cells 26. Thus, memory's internal data strobe signal (the DQS signal) 39 is derived from the external strobe signal XDQS 19. Further, as seen from the circuit configuration in FIG. 2, each of the data bits is output on one of the edges—rising edge or falling edge—of the DQS signal 39. Thus, the circuit configuration in FIG. 2 may be used to write data into a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) chip.
FIG. 3 depicts a typical XDQS signal 19 and an exemplary memory data write operation using the XDQS signal 19 as the data strobe signal. The XDQS signal 19, per its specification, may contain a preamble ringing 42 and a postamble ringing 44. Although the signals in the preamble and postamble ringings 42, 44 are shown as triangular waves, it is understood that these signals may have any form—sinusoidal, triangular, sawtooth, random etc. Further, as is known in the art, the signal level of the XDQS signal 19 during these pre- and post-amble ringings 42, 44, is undefined. However, after preamble ringing 42 is over, the XDQS signal 19 stabilizes and transitions in synchronism with the system clock (not shown). The lined portion in the data waveform in FIG. 3 indicates unknown state of the data pin. The data bits may be valid only during certain times. In FIG. 3, the data bits 0–4 on the external data pin (XDQ) 18 are shown to appear in appropriate timing relationship with the XDQS signal's rising and falling edges. The XDQS signal 19 may keep toggling (in synchronism with the system clock (not shown)) until all data bits are written. For example, in FIG. 3, only four data bits are to be written and, hence, the XDQS signal 19 remains “active” for two cycles to strobe four data bits into the memory cells 26—one data bit on each of the two rising and two falling edges.
As is known to one skilled in the art, the specification for the XDQS signal 19 defines a postamble time 46 as the time for which the XDQS signal 19 remains in a “low” state after the last bit of data (e.g., Bit 3 in FIG. 3) is clocked in. After the postamble time 46, however, the state of XDQS 19 is no longer guaranteed and it could assume any value. After the postamble time 46, the postamble ringing 44 may start and any such ringing on XDQS 19 may cause erroneous bits of data to be clocked in because the postamble ringing 44 may be erroneously recognized by the data latching flipflops (e.g., the flipflops 36 and 38 in FIG. 2) as valid data clocking edges (or edge transitions) of the XDQS signal 19. But, as shown in FIG. 3, during the postamble ringing period 44, the state of data signals on the data pin XDQ 18 is unknown because the last bit of data (e.g., Bit 3 in FIG. 3) is already written and there is no more data to write. Therefore, any triggering of data flipflops by postamble ringing will result in incorrect data bits to be written into memory cells.
To avoid accidental triggering of data flipflops 36, 38 during postamble ringing 44 (and, hence, to avoid incorrect data outputs to be sent to memory cells 26), the data writing circuitry in FIG. 2 turns “off” or deactivates the Enable control 40 during the postamble time 46 so as to effectively prevent the application of the XDQS signal 19 (and its postamble ringing 44) to the data flipflops 36, 38 via the DQS signal 39. Thus, the Enable control 40 prevents the DQS signal 39 from having the postamble ringing 44 of the XDQS signal 19. However, this approach may be well suited for slower speed DDR SDRAM memory chips, where the postamble time 46 may be in the range of 3–5 nanoseconds (ns). In the modern, faster DDR2 and DDR3 SDRAM chips, the clock periods of the system clocks themselves are in the range of 2.5 to 3 ns. Such DDR2 and DDR3 chips, in turn, require correspondingly shorter postamble time 46 because the postamble time 46 is typically equal to 0.4 tCK (where “tCK ” represents the clock period of the system clock) per XDQS specification. Therefore, in such faster versions of DDR SDRAM chips, the postambe time 46 would be typically in the range of 1 to 1.2 ns. This time of 1–1.2 ns may be too short for the Enable control 40 to turn off the buffer 34 in time prior to onset of postamble ringing 44 because of the very high frequency of XDQS 19 and DQS 39 signals. The high frequency DQS signal 39 may be itself 0.25tCK early or late with reference to the system clock. Therefore, the effective time for the buffer 34 to act prior to postamble ringing 44 is even less than 1–1.2 ns.
It is thus seen that the current buffer-based control of DQS postamble ringing may not be effective in itself, especially when modern memory chips are operated at ever faster clock speeds. Therefore, it is desirable to devise a scheme whereby DQS postamble ringing problem in higher speed memory chips is significantly reduced or eliminated so that false data may not get “clocked in” or written into the memory chip because of postamble ringing. The prevention of data corruption and preservation of integrity of data written into a memory chip is also desirable.